B.TECH. IN ELECTRONICS ENGINEERING (VLSI DESIGN AND TECHNOLOGY)coretheorySem 3
VERIFICATION USING SYSTEM VERILOG
ECE 3130
Syllabus
- 01Introduction to verification
- 02Developing Verification strategies
- 03Applying Verification strategies
- 04RTL ports and interfaces
- 05Modelling hardware interfaces with concurrency constructs
- 06simulating test benches using Fork-join
- 07stimulus synchronization using conventional synchronization constructs like Mailboxes, Semaphores, regions and events
- 08System Verilog
- 09Advanced Functional Verification
- 10Basics of Formal Verification
- 11Verification of combinational and sequential logic circuits using System Verilog
References
- Padmanabhan T.R. and Sundari B.B.T., Design Through Verilog HDL, John Wiley &Sons, 2004.
- Palnitkar S., Verilog® HDL. A Guideto Digital Designand Synthesis IEEE 1361-2001 Compliant (2e), Prentice Hall,2003
- Bhaskar J., A VerilogHDL Primer, BS Publications, 2005.
- Brown S..and Vranesic Z., Fundamentals of Digital Logic with VerilogDesign (5e), Tata McGraw Hill, 2005.
- Ciletti M.D., Advanced DigitalDesign with theVerilog HDL, PHI, 2005.
Credits Structure
3Lecture
0Tutorial
0Practical
3Total